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? semiconductor components industries, llc, 2008 october, 2008 ? rev. 31 1 publication order number: ncv8502/d ncv8502 series micropower 150 ma ldo linear regulators with delay, adjustable reset , and monitor flag the ncv8502 is a family of precision micropower voltage regulators. their output current capability is 150 ma. the family has output voltage options for adjustable, 2.5 v, 3.3 v, 5.0 v, 8.0 v, and 10 v. the output voltage is accurate within 2.0% with a maximum dropout voltage of 0.6 v at 150 ma. low quiescent current is a feature drawing only 90 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset (with delay), and a flag monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. the use of the flag monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. the reset threshold voltage can be decreased by the connection of external resistor divider to r adj lead. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. the device has also been optimized for emc conditions. features ? output voltage options: adjustable, 2.5 v, 3.3 v, 5.0 v, 8.0 v, 10 v ? 2.0% output ? low 90 a quiescent current ? fixed or adjustable output voltage ? active reset ? adjustable reset ? 150 ma output current capability ? fault protection ? +60 v peak transient voltage ? ? 15 v reverse voltage ? short circuit ? thermal overload ? early warning through flag /mon leads ? ncv prefix for automotive and other applications requiring site and change control ? aec qualified ? ppap capable ? these are pb ? free devices so ? 8 d suffix case 751 see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information soic 16 lead wide body exposed pad pdw suffix case 751ag 1 16 http://onsemi.com marking diagrams sow ? 16 e pad so ? 8 x = voltage ratings as indicated below: a = adjustable 2 = 2.5 v 3 = 3.3 v 5 = 5.0 v 8 = 8.0 v 0 = 10 v a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free device 1 16 8502x awlyywwg 8502x alyw 1 8 1 8
ncv8502 series http://onsemi.com 2 gnd nc 18 flag nc v adj mon v out v in pin connections, adjustable output so ? 8 gnd delay 18 reset r adj flag mon v out v in pin connections, fixed output so ? 8 nc mon 1 16 nc v in nc nc nc nc gnd nc nc nc nc v out flag v adj sow ? 16 e pad r adj mon 1 16 delay v in nc nc nc nc gnd nc nc nc nc v out reset flag sow ? 16 e pad v out gnd v in r adj ncv8502 10 f 10 k r rst reset 10 f microprocessor delay c delay v bat v dd flag figure 1. application diagram mon r flg 10 k v adj (adjustable output only) i/o i/o maximum ratings* rating value unit v in (dc) ? 15 to 48 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v operating voltage 45 v v out (dc) ? 0.3 to 16 v voltage range (reset , flag ) ? 0.3 to 10 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *during the voltage range which exceeds the maximum tested voltage of v in , operation is assured, but not specified. wider limits may apply. thermal dissipation must be observed closely.
ncv8502 series http://onsemi.com 3 maximum ratings* (continued) rating symbol value unit input voltage range (mon, v adj , r adj ) ? 0.3 to 10 v esd susceptibility (human body model) 2.0 kv junction temperature t j ? 40 to +150 c storage temperature t s ? 55 to 150 c package thermal resistance, so ? 8: junction ? to ? case junction ? to ? ambient r jc r ja 45 165 c/w c/w package thermal resistance, sow ? 16 e pad: junction ? to ? case junction ? to ? ambient junction ? to ? pin (note 1) r jc r ja r jp 15 56 35 c/w c/w c/w lead temperature soldering: smd style only, reflow (note 2) pb ? free part 60 ? 150 sec above 217 c, 40 sec max at peak sld 265 peak c 1. measured to pin 16. 2. per ipc / jedec j ? std ? 020c. *during the voltage range which exceeds the maximum tested voltage of v in , operation is assured, but not specified. wider limits may apply. thermal dissipation must be observed closely. electrical characteristics (i out = 1.0 ma, ? 40 c t j 150 c; v in = dependent on voltage option (note 3); unless otherwise specified.) characteristic test conditions min typ max unit output stage output voltage for 2.5 v option 6.5 v < v in < 16 v, 100 a i out 150 ma 5.5 v < v in < 26 v , 100 a i out 150 ma 2.450 2.425 2.5 2.5 2.550 2.575 v v output voltage for 3.3 v option 7.3 v < v in < 16 v, 100 a i out 150 ma 5.5 v < v in < 26 v , 100 a i out 150 ma 3.234 3.201 3.3 3.3 3.366 3.399 v v output voltage for 5.0 v option 9.0 v < v in < 16 v, 100 a i out 150 ma 6.0 v < v in < 26 v , 100 a i out 150 ma 4.90 4.85 5.0 5.0 5.10 5.15 v v output voltage for 8.0 v option 9.0 v < v in < 26 v , 100 a i out 150 ma 7.76 8.0 8.24 v output voltage for 10 v option 11 v < v in < 26 v , 100 a i out 150 ma 9.7 10 10.3 v v output voltage for adjustable option v out = v adj (unity gain) 6.5 v < v in < 16 v, 100 a < i out < 150 ma 5.5 v < v in < 26 v, 100 a < i out < 150 ma 1.254 1.242 1.280 1.280 1.306 1.318 v v dropout voltage (v in ? v out ) (5.0 v, 8.0 v, 10 v and adj. > 5.0 v options only) i out = 150 ma i out = 1.0 ma ? ? 400 100 600 150 mv mv load regulation v in = 14 v, 5.0 ma i out 150 ma ? 30 5.0 30 mv line regulation [v out (typ) + 1.0] < v in < 26 v, i out = 1.0 ma ? 15 60 mv quiescent current, low load 2.5 v option 3.3 v option 5.0 v option 8.0 v option 10 v option adjustable option i out = 100 a, v in = 12 v, mon = v out ? ? ? ? ? ? 90 90 90 100 100 50 125 125 125 150 150 75 a a a a a a quiescent current, medium load all options i out = 75 ma, v in = 14 v, mon = v out ? 4.0 6.0 ma quiescent current, high load all options i out = 150 ma, v in = 14 v, mon = v out ? 12 19 ma current limit ? 151 300 ? ma 3. voltage range specified in output stage of the electrical characteristics in boldface type.
ncv8502 series http://onsemi.com 4 electrical characteristics (continued) (i out = 1.0 ma; ? 40 c t j 150 c; v in = dependent on voltage option (note 4); unless otherwise specified.) characteristic test conditions min typ max unit output stage short circuit output current v out = 0 v 40 190 ? ma thermal shutdown (guaranteed by design) 150 180 ? c reset function (reset) reset threshold for 2.5 v option high (v rh ) low (v rl ) 5.5 v v in 26 v (note 5) v out increasing v out decreasing 2.28 2.25 2.350 2.300 0.98 v out 0.97 v out v v reset threshold for 3.3 v option high (v rh ) low (v rl ) 5.5 v v in 26 v (note 5) v out increasing v out decreasing 3.00 2.97 3.102 3.036 0.98 v out 0.97 v out v v reset threshold for 5.0 v option high (v rh ) low (v rl ) v out increasing v out decreasing 4.55 4.50 4.70 4.60 0.98 v out 0.97 v out v v reset threshold for 8.0 v option high (v rh ) low (v rl ) v out increasing v out decreasing 7.05 7.00 7.52 7.36 0.98 v out 0.97 v out v v reset threshold for 10 v option high (v rh ) low (v rl ) v out increasing v out decreasing 8.60 8.50 9.40 9.20 0.98 v out 0.97 v out v v output voltage low (v rlo ) 1.0 v v out v rl , r reset = 10 k ? 0.1 0.4 v delay switching threshold (v dt ) ? 1.4 1.8 2.2 v delay low voltage v out < reset threshold low(min) ? ? 0.1 v delay charge current delay = 1.0 v, v out > v rh 1.5 2.5 3.5 a delay discharge current delay = 1.0 v, v out = 1.5 v 5.0 ? ? ma reset adjust switching voltage (v r(adj) ) ? 1.23 1.31 1.39 v flag /monitor monitor threshold increasing and decreasing 1.10 1.20 1.31 v hysteresis ? 20 50 100 mv input current mon = 2.0 v ? 0.5 0.1 0.5 a output saturation voltage mon = 0 v, i flag = 1.0 ma ? 0.1 0.4 v voltage adjust (adjustable output only) input current v adj = 1.28 v ? 0.5 ? 0.5 a 4. voltage range specified in output stage of the electrical characteristics in boldface type. 5. for v in 5.5 v, a reset = low may occur with the output in regulation.
ncv8502 series http://onsemi.com 5 package pin description, adjustable output package pin number pin symbol function so ? 8 sow ? 16 e pad 1 7 v in input voltage. 2 8 mon monitor. input for early warning comparator. if not needed connect to v out. 3, 4 3 ? 6, 9 ? 12, 14, 15 nc no connection. 5 13 gnd ground. all gnd leads must be connected to ground . 6 16 flag open collector output from early warning comparator. 7 1 v adj voltage adjust. a resistor divider from v out to this lead sets the output voltage. 8 2 v out 2.0%, 150 ma output. package pin description, fixed output package pin number pin symbol function so ? 8 sow ? 16 e pad 1 7 v in input voltage. 2 8 mon monitor. input for early warning comparator. if not needed connect to v out. 3 9 r adj reset adjust. if not needed connect to ground. 4 10 delay timing capacitor for reset function. 5 13 gnd ground. all gnd leads must be connected to ground . 6 16 reset active reset (accurate to v out 1.0 v) 7 1 flag open collector output from early warning comparator. 8 2 v out 2.0%, 150 ma output. ? 3 ? 6, 11, 12, 14, 15 nc no connection.
ncv8502 series http://onsemi.com 6 typical performance characteristics ? 40 v out (v) 4.98 temperature ( c) 4.99 5.00 5.01 ? 25 ? 10 125 5 203550658095110 v out = 5.0 v v in = 14 v i out = 5.0 ma figure 2. output voltage vs. temperature ? 40 v out (v) 3.27 temperature ( c) 3.32 3.33 3.35 ? 25 ? 10 125 5 203550658095110 3.34 3.29 3.30 3.31 3.28 v out = 3.3 v v in = 14 v i out = 5.0 ma figure 3. output voltage vs. temperature figure 4. quiescent current vs. output current figure 5. quiescent current vs. output current +25 c ? 40 c 0 i q (ma) 0 i out (ma) 0.2 0.4 0.6 0.8 1.0 1.2 510152025 +125 c v in = 12 v 0 i q (ma) 0 i out (ma) 2 4 6 8 10 12 14 15 30 45 60 140 75 90 105 120 135 +25 c ? 40 c +125 c v in = 12 v 6 i q (ma) 0 v in (v) 1 2 3 4 5 6 7 8101214 26 16 18 20 22 24 i out = 10 ma i out = 50 ma i out = 100 ma t = 25 c figure 6. quiescent current vs. input voltage figure 7. quiescent current vs. input voltage i out = 100 a 6 i q ( a) 0 v in (v) 20 49 60 80 100 120 8101214 26 16 18 20 22 24 t = 25 c
ncv8502 series http://onsemi.com 7 typical performance characteristics +25 c ? 40 c +125 c 0 dropout voltage (mv) 0 i out (ma) 150 200 250 300 350 400 450 25 50 75 100 150 50 100 125 figure 8. dropout voltage vs. output current v out = 5.0 v, 8.0 v, or 10 v 0.01 0.1 1.0 10 100 1000 0 102030405060708090100 output current (ma) esr ( ) c vout = 10 f 10 v 8 v 5 v 3.3 v 2.5 v figure 9. output stability with output voltage change unstable region stable region figure 10. output stability with output capacitor change 0.01 0.1 1.0 10 100 1000 0 102030 5060708090100110 output current (ma) esr ( ) c vout = 10 f c vout = 0.1 f unstable region stable region 40
ncv8502 series http://onsemi.com 8 v in reset v out flag r adj delay figure 11. block diagram gnd mon current source (circuit bias) current limit sense error amplifier v bg i bias v bg v bg i bias i bias v bg i bias + ? + ? + ? + ? + bandgap reference thermal protection 1.8 v 3.0 a 20 k adjustable version only v adj fixed voltage only
ncv8502 series http://onsemi.com 9 circuit description regulator control functions the ncv8502 contains the microprocessor compatible control function reset (figure 12). figure 12. reset and delay circuit wave forms v in v out reset delay (v dt ) threshold delay threshold reset t d t d reset function a reset signal (low voltage) is generated as the ic powers up until v out is within 6.0% of the regulated output voltage, or when v out drops out of regulation,and is lower than 8.0% below the regulated output voltage. hysteresis is included in the function to minimize oscillations. the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic thereby guaranteeing that the reset signal is valid for v out as low as 1.0 v. adjustable reset function the reset threshold can be made lower by connecting an external resistor divider to the r adj lead from the v out lead, as displayed in figure 13. this lead is grounded to select the default value of 4.6 v. figure 13. adjustable reset r adj to p and system power r rst v out c out reset c delay delay ncv8502 to p and reset port delay function the reset delay circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current (typically 2.5 a) to the external delay capacitor during the following proceedings: 1. during power up (once the regulation threshold has been verified). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is discharged when the regulation (reset threshold) has been violated. this is a latched incident. the capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. flag /monitor function an on ? chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. the reset signal typically turns the microprocessor off instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the flag pin will allow the microprocessor time to complete its present task before shutting down. this function is performed by a comparator referenced to the bandgap reference. the actual trip point can be programmed externally using a resistor divider to the input monitor (mon) (figure 14). the typical threshold is 1.20 v on the mon pin. figure 14. flag /monitor function v bat v in mon v out c out v cc i/o reset p flag reset gnd delay ncv8502 r adj voltage adjust figure 15 shows the device setup for a user configurable output voltage. the feedback to the v adj pin is taken from a voltage divider referenced to the output voltage. the loop is balanced around the unity gain threshold (1.28 v typical). figure 15. adjustable output voltage v out v adj ncv8502 15 k 5.1 k c out 5.0 v 1.28 v
ncv8502 series http://onsemi.com 10 application notes figure 16. additional output current ncv8502 v in v out v adj c2 0.1 f v bat 5.0 v mjd31c r1 294 k r2 100 k c1 47 f >1 amp adding capability figure 16 shows how the adjustable version of parts can be used with an external pass transistor for additional current capability. the setup as shown will provide greater than 1 amp of output current. flag monitor figure 17 shows the flag monitor waveforms as a result of the circuit depicted in figure 14. as the output voltage falls (v out ), the monitor threshold is crossed. this causes the voltage on the flag output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t wa r n i n g is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. figure 17. flag monitor circuit waveform v out mon reset flag monitor ref. voltage t warning flag figure 18. test and application circuit showing output compensation v in v out c out ** 10 f r rst reset c in * 0.1 f ncv8502 *c in required if regulator is located far from the power supply filter **c out required for stability. capacitor must operate at minimum temperature expected setting the delay time the delay time is controlled by the reset delay low voltage, delay switching threshold, and the delay charge current. the delay follows the equation: t delay c delay (v dt reset delay low voltage) delay charge current example: using c delay = 33 nf. assume reset delay low voltage = 0. use the typical value for v dt = 1.8 v. use the typical value for delay charge current = 2.5 a. t delay 33 nf(1.8 0) 2.5 a 23.8 ms stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: start ? up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. the value for the output capacitor c out shown in figure 18 should work for most applications, however it is not necessarily the optimized solution.
ncv8502 series http://onsemi.com 11 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 19) is: p d(max) [v in(max) v out(min) ]i out(max) v in(max) i q (eq. 1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (eq. 2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? i q control features i out i in figure 19. single output regulator with key performance parameters labeled v in v out } figure 20. 16 lead sow (exposed pad), ja as a function of the pad copper area (2 oz. cu thickness), board material = 0.0625 g ? 10/r ? 4 40 70 90 100 thermal resistance, junction to ambient, r ja , ( c/w) 0 copper area (mm 2 ) 200 400 800 80 60 50 600 heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (eq. 3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
ncv8502 series http://onsemi.com 12 ordering information device output voltage package shipping ? ncv8502dadjg adjustable so ? 8 (pb ? free) 98 units/rail ncv8502dadjr2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdwadjg sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8502pdwadjr2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8502d25g 2.5 v so ? 8 (pb ? free) 98 units/rail ncv8502d25r2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdw25g sow ? 16 exposed pad (pb ? free) 47 units/rail NCV8502PDW25R2G sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8502d33g 3.3 v so ? 8 (pb ? free) 98 units/rail ncv8502d33r2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdw33g sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8502pdw33r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8502d50g 5.0 v so ? 8 (pb ? free) 98 units/rail ncv8502d50r2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdw50g sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8502pdw50r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8502d80g 8.0 v so ? 8 (pb ? free) 98 units/rail ncv8502d80r2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdw80g sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8502pdw80r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8502d100g 10 v so ? 8 (pb ? free) 98 units/rail ncv8502d100r2g so ? 8 (pb ? free) 2500 tape & reel ncv8502pdw100g sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8502pdw100r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ?for information on tape and reel specifications, includin g part orientation and tap e sizes, please refer to our tape and reel packaging spe- cification brochure, brd8011/d.
ncv8502 series http://onsemi.com 13 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncv8502 series http://onsemi.com 14 package dimensions soic 16 lead wide body, exposed pad pdw suffix case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8502/d smart regulator is a registered trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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